HD66760 Datasheet, PDF (47/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
a) Basic data-receive timing through the clock synchronized serial interface
Transfer start
CS*
Transfer end
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDA
"0" "1" "1" "1" "0" ID RS "0" D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Device ID code
RS RW
1st index or data
2nd index or data
Start byte
b) 1st and 2nd byte assignment
1st byte
D7 D6 D5 D4 D3 D2 D1 D0
Index register / write data register
2nd byte
D7 D6 D5 D4 D3 D2 D1 D0
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
Index / write data register
upper bits
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Index / write data register
lower bits
c) Consecutive data-receive timing through the clock synchnorized serial interface
CS*
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SDA
Start byte
Index / write data
register upper bits
Index / write data
register lower bits
Index / write data
register upper bits
Index / write data
register lower bits
2 bytes
2 bytes
Index / write data register execution.
note:
- After start byte transfer, upper bits of the index or write data register should be written first.
- Start byte should be transfered first.
- Index or write data register is executed when upper and lower bits are written.
Therefore, data transfer unit has to be twice byte access cycle.
Index / write data
register execution.
Figure 30a Clock synchronized serial interface data-receive sequence