HD66760 Datasheet, PDF (46/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
Serial Data Transfer (Clock synchronized serial interface)
Setting the IM2=Vcc and IM1=GND level allows standard clock synchronized serial data transfer, using the
chip select line (CS*), serial data line (SDA) and serial transfer clock line (SCL). For the clock synchronized
serial interface, the IM0/ID pin function uses an ID pin.
The HD66760 initiates clock synchronized serial data transfer by transferring the first byte at the falling edge
of CS* input. It ends clock synchronized serial data transfer the rising edge of CS* input.
The HD66760 is selected when the higher 6-bit slave address in the first byte transferred from the transmitting
device match the 6-bits device identification code assigned to the HD66760. The HD66760, when selected,
receive the subsequent data string. The lower 1-bit of the device identification code can be determined by the
ID pin. The upper five bits are fixed to 01110. Two different chip address must be assigned to a single
HD66760 because the seventh bit of the start byte is used as a register select bit (RS); that is, when RS=0, an
index can be written, and when RS=1, control register and GRAM data can be written or read from GRAM.
Read or write is selected according to the eighth bit of the start byte (R/W bit). The data is received when the
R/W bit is 0, and is transmitted when the R/W bit is 1.
After receiving the start byte, the HD66760 receives the subsequent data as an HD66760 index or as GRAM
data.
Five bytes of GRAM read data after the start byte are invalid. The HD66760 start to read correct GRAM data
from sixth byte.
Table 30a Start Byte Format
Transfer Bit
Start byte format
S
Transfer start
Note: ID bit is selected by the IM0/ID pin.
1
2
3
4
5
6
7
8
Device ID code
RS R/W
0
1
1
1
0
ID
Table 30b RS and R/W bit function
RS R/W Function
0
0
Write index register to index
0
1
Reads status
1
0
Write control register or GRAM via write data register
1
1
Read GRAM via read data register