HD66760 Datasheet, PDF (90/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
68-system Bus Interface Timing Characteristics
(Vcc = 2.2 to 2.4 V)
Item
Symbol Min
Enable cycle time
Write t_CYCE
600
Read t_CYCE
800
Enable high-level pulse width Write PW_EH 120
Read PW_EH 350
Enable low-level pulse width
Write PW_EL 300
Read PW_EL 400
Enable rise/fall time
t_Er, t_Ef
—
Setup time (RS, R/W to E, CS*)
t _ASE
10
Address hold time
t _AHE
20
Write data setup time
t _DSWE
60
Write data hold time
t _HE
20
Read data delay time
t _DDRE
—
Read data hold time
t _DHRE
5
Typ Max Unit Test Condition
—
—
ns
Figure 67
—
—
—
—
ns
Figure 67
—
—
—
—
ns
Figure 67
—
—
—
25
ns
Figure 67
—
—
ns
Figure 67
—
—
ns
Figure 67
—
—
ns
Figure 67
—
—
ns
Figure 67
—
300 ns
Figure 67
—
—
ns
Figure 67
(Vcc = 2.4 to 3.6 V)
Item
Symbol Min Typ
Enable cycle time
Write t_CYCE
300 —
Read t_CYCE
500 —
Enable high-level pulse width Write PW_EH 70 —
Read PW_EH 250 —
Enable low-level pulse width
Write PW_EL 100 —
Read PW_EL 200 —
Enable rise/fall time
t_Er, t_Ef
—
—
Setup time (RS, R/W to E, CS*)
t _ASE
10 —
Address hold time
t _AHE
5
—
Write data setup time
t _DSWE
60
—
Write data hold time
t _HE
15 —
Read data delay time
t _DDRE
—
—
Read data hold time
t _DHRE
5
—
Max Unit
—
ns
—
—
ns
—
—
ns
—
25
ns
—
ns
—
ns
—
ns
—
ns
200 ns
—
ns
Test Condition
Figure 67
Figure 67
Figure 67
Figure 67
Figure 67
Figure 67
Figure 67
Figure 67
Figure 67
Figure 67