HD49323AF Datasheet, PDF (8/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
3. AGC Circuit
The AGC gain is set by means of 11-bit serial data. The setting range is –3.3 dB to 34.7 dB. Details of
the data are given in the following section.
The (–) side gain setting uses setting codes –81 to 0 in 0.0039-multiple steps, and the (+) side gain
setting uses setting codes 0 to 1023 in 0.034 dB steps.
• Detailed specifications of HD49323AF-01 AGC gain setting codes
(1) To improve S/N, the AD input dynamic range has been extended to 1.4 V from the 1.0 V of the
HD49322BF.
(2) There are two AGC gain ranges: (+) side 0 to 34.7 dB linear gain amp. (0.034 dB/step), and (–) side
0 to –3.3 dB “multiple” linear gain amp. (0.0039 multiple/step).
Input
CDS
AGC
Range
Typ 1.4V
0V = 0 code
ADC
0.7V = 511 code
1.4V = 1023 code
Output
Considering the case where AGC gain is set so that the ADC output code is 511 when a 150 mV signal is
input:
 The HD49322BF AGC gain setting is (code 511)/150 mV multiple = 500 mV/150 mV multiple
 The HD49323AF-01 AGC gain setting is (code 511)/150 mV multiple = 700 mV/150 mV multiple
Table 1 AGC Gain (+) Setting Code Table
Code
0
1
2
3
⋅⋅⋅
510
511
512
513
⋅⋅⋅
1020
1021
1022
1023
BIN (D10 to D0)
000 0000 0000
000 0000 0001
000 0000 0010
000 0000 0011
001 1111 1110
001 1111 1111
010 0000 0000
010 0000 0001
011 1111 1100
011 1111 1101
011 1111 1110
011 1111 1111
dB
0.000
0.034
0.068
0.102
17.34
17.37
17.41
17.44
34.68
34.71
34.75
34.78
Table 2 AGC Gain (−) Setting Code Table
Code
0
−1
−2
−3
⋅⋅⋅
−30
−31
−32
−33
⋅⋅⋅
−78
−79
−80
−81
BIN (D10 to D0) Multiple dB
000 0000 0000 1.000 0.000
111 1111 1111 0.996 −0.034
111 1111 1110 0.992 −0.068
111 1111 1101 0.988 −0.102
111 1110 0010
111 1110 0001
111 1110 0000
111 1101 1111
0.883
0.879
0.875
0.871
−1.083
−1.121
−1.160
−1.199
111 1011 0010
111 1011 0001
111 1011 0000
111 1010 1111
0.695
0.691
0.688
0.684
−3.156
−3.205
−3.255
−3.304
4. Offset cancel circuit
When power is turned on, offset voltages generated by CDS, AGC, ADC, and other circuits by means
of serial data control are canceled. (Refer to page 24 (Operating Sequence at Power-On).)
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