HD49323AF Datasheet, PDF (23/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
14. If the phase difference between the black level sampling voltage and the signal level sampling voltage
during the CCD imaging element optical black period (the CCD offset voltage) is ±30 mV or greater,
the CCD offset cancel function (page 9, item 7, CCD Offset Cancel Function) must be implemented.
The CCD offset voltage variation after implementation of the CCD offset cancel function should be
within ±20 mV.
15. The CDSIN pin is clamped at VRM (≅ AV_DD/2) during operation. The IC may suffer permanent
damage if used with a pin voltage in the range –0.3 V to AV_DD + 0.3 V. Careful attention must
therefore be paid to the input signals.
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