HD49323AF Datasheet, PDF (14/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
Detailed Timing Specifications for Pre-Blanking
Detailed timing specifications for pre-blanking are shown in figure 6. When the PBLK pin is high, digital
output is fixed at 32 LSB. However, the OE pin and serial data output mode settings (LINV, MINV,
TEST, STBY) take precedence.
PBLK
1.4V
×
DV_DD
3.0V
V_OH
Digital output
(D0 to D9)
t_PBLK
t_PBLK
V_OL
Figure 6 Detailed Timing Specifications for Pre-Blanking
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