HD49323AF Datasheet, PDF (13/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
Table 5 Each Timing Specifications
No. Timing
Symbol Min
Typ
Max
Unit Note
(1)
Black level signal read-in time t_CDS1
0
5
10
ns
1
(2)
SPBLK “Lo” period
t _CDS2
11
1/4f_ADCLK
Typ × 1.2 ns
2
(3)
Signal level read-in time
t _CDS3
0
5
10
ns
1
(4)
SPSIG “Lo” period
t _CDS4
11
1/4f_ADCLK
Typ × 1.2 ns
2
(5)
SPBLK rise to SPSIG rise
t _CDS5
20
1/2f_ADCLK
Typ × 1.15 ns
2
(6)-1 ADCLK rise to SPBLK rise
t _CDS6-1
25
—
—
ns
2
(6)-2 SPSIG rise to ADCLK rise
t _CDS6-2
0
ns
2
(7), (8) ADCLK t_WH Min / t_WL Min
t_{CDS7, 8}
22
ns
Note: 1. Negative when data before the rising edge of SPBLK/SPSIG is sampled, and positive when data
after the rising edge is sampled.
2. The polarity of SPBLK and SPSIG is for a low setting of the serial data SP INV bit.
SPBLK
SPSIG
1.4V
−+
Detailed Timing Specifications for Digital Output Enable Control
Detailed timing specifications in the case of digital output enable control are shown in figure 5. When the
OE pin is high, output disable mode is entered and output goes to the high-Z state.
OE
Digital output
t_LZ
(D0 to D9)
t_HZ
DV_DD/2
t_ZL
DV_DD/2
t_ZH
1.4V
×
DV_DD
3.0V
DV_DD
V_OL
V_OH
DV_SS
t_LZ, t_ZL
measurement load
DV_DD
2kΩ
10pF
DV_SS
t_HZ, t_ZH
measurement load
10pF 2kΩ
DV_SS DV_SS
Figure 5 Detailed Timing Specifications for Digital Output Enable Control
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