HD49323AF Datasheet, PDF (7/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
Internal Functions
Functional Description
• CDS (Correlated Double Sampling) circuit
• AGC gain selection (11-bit digital control) *¹
 AGC gain can be set in the range 0 dB to 34.7 dB on the (+) side, and –3.3 dB to 0 dB on the (–)
side by means of 11-bit serial data.
• Automatic offset adjustment is possible for the IC’s offsets (CDS, AGC, ADC) by means of serial data
control at power-on.*¹
• Digital output enable function
• Pre-blanking function
 Digital output can be fixed at 32 LSB
• CDS offset cancel function
Note: 1. Serial data control
Operating Description
Figure 1 shows CDS/AGC +ADC function block.
TESTC
TESTY
CDSIN
CDS
AGC
Gain
select
Serial interface
10bit
ADC
Offset
cancel
D0 to D9
SPBLK SPSIG CS SCK SDATA ADCLK
Figure 1 CDS/AGC +ADC Function Block
1. CDS (Correlated Double Sampling) Circuit
The CCD imaging element alternately outputs a black level (A-period signal) and a signal including the
black level (B-period signal). The CDS circuit extracts the differential voltage between the black level
and the signal including the black level (see figure 4).
Black level sampling is performed at the rising edge of the SPBLK pulse, and signal level sampling is
performed at the rising edge of the SPSIG pulse. This sequence of operations extracts the differential
voltage between the black level and the signal including the black level, and supplies this to the next-
stage AGC circuit.
2. Feed back clamp function
The clamp level is set by means of 5-bit serial data. The setting range is 32 LSB to 56 LSB, in 1 LSB
steps. A serial data value of 0 gives a 32 LSB setting, and a value of 24 gives a 56 LSB setting.
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