HD49323AF Datasheet, PDF (24/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
Operating Sequence at Power-On
Must be stabilized within operating
power supply voltage range
V_DD
0ms
or
0ms
or
0ms
or
1V(16ms)
4V(64ms)
0ms
or
more more more or more
or more
more
RESET
OFRST
(2) RESET = "Hi"
(1) RESET = "Lo"
(4) OFRST = "Hi"
(5) OFRST = "Lo"
HD49323AF
data transfer
(3) Data transfer
(6) Data
transfer
SPBLK
TG and
SPSIG
Camera DSP _ADCLK
control start _OBP
etc.
0ms
or more
Note: 1. RESET and OFRST both use serial data transmission.
2. Stable input of SPBLK, SPSIG, ADCLK, and OBP is assumed before RESET is transmitted.
3. Numbers in parentheses in the figure show the order of transfer.
Figure 8 Operating Sequence at Power-On
Serial data transmission contents are shown in table 9.
“X” indicates data for which the clock polarity, clamp level, etc., can be selected. See page 21 (table 8,
Serial Data Functions Table) for the purpose of the data.
Table 9 Serial Data
Order of Transfer
(1) RESET = "Lo"
(2) RESET = "Hi"
(3) Data transfer
Wait
(4) OFRST = "Hi"
Wait
(5) OFRST = "Lo"
(6) Data transfer
MSB
Serial Data (DI)
LSB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Remarks
a) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
b) 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1
c) 0 0 1 0 0 0 X X X X X X X X 0 1
d) 1 1 1 0 1 0 0 0 0 X X X X X 1 0
1 V (16 ms) or more
e) 0 1 1 0 0 0 X X X X X X X X 0 1
4 V (64 ms) or more
f) 0 0 1 0 0 0 X X X X X X X X 0 1
g) 0 X X X X X X X X X X X X X 0 0
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