HD49323AF Datasheet, PDF (15/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
Output Code Table
Table 6 Function Table
Digital Output
OE STBY TEST LINV MINV PBLK D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation Mode
H X X X X X Hi-Z
Output Hi-Z
L H X X X X Hi-Z
Low power standby
L L L L L Table 7 as follows
Normal operation
L H L In the table 7 below, D9 is inverted
H L L In the table 7 below, D8 to D0 are inverted
H H L In the table 7 below, D9 to D0 are inverted
L L H L L L L H L L L L L Pre-blanking
H L L X L H L H L H L H L H Test mode
L H X HHLHLHLHLH
H L X LLHLHLHLHL
H H X HLHLHLHLHL
Note:
1. STBY, TEST, LINV, and MINV mode setting is performed by means of serial data.
2. OE and PBLK mode setting is performed by means of external input pins.
3. Pre-blanking mode is enabled when the PBLK pin is high and all other pins are low.
Table 7 Output Code Table
Output Pin
Output Step
code
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Input Level
0 L L L L L L L L L L →0V
1L L L L L L L L L H
2L L L L L L L L H L
3L L L L L L L L H H
511 L H H H H H H H H H →0.7V
512 H L L L L L L L L L
1020 H H H H H H H H L L
1021 H H H H H H H H L H
1022 H H H H H H H H H L
1023 H H H H H H H H H H →1.4V
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