HD49323AF Datasheet, PDF (11/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

Timing Chart
Figure 3 shows the output timing.
HD49323AF-01
• Sampling timing chart
0
1
2
3
4
5
6
CDSIN
N
N+1
N+2
N+3
N+4
N+5
N+6
SPBLK
SPSIG
ADCLK
D0 to D9
N−5
N−4
N−3
N−2
N−1
N
Figure 3 Output Timing
• The ADC output signals (D0 to D9) are output at the rising edge of ADCLK.
• The pipeline delay is 5 clocks.
• Regarding OBP
H period
OBP > 12fs
Note: The phase of OBP is for a low setting of the serial data OBP INV bit.
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