HD49323AF Datasheet, PDF (21/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

Table 8 Serial Data Functions Table
HD49323AF-01
Resister 0
Resister 1
Resister 2
Resister 3
DI 00 (LSB)
Lo
Hi
Lo
Hi
DI 01
DI 02
DI 03
DI 04
DI 05
DI 06
DI 07
DI 08
DI 09
DI 10
Lo
AGC Gain setting (LSB)
AGC Gain setting
AGC Gain setting
AGC Gain setting
AGC Gain setting
AGC Gain setting
AGC Gain setting
AGC Gain setting
AGC Gain setting
Lo
SP INV SPSIG/SPBLK
inversion
OBP INV
Lo→Negative input
Hi→Positive input
CIF
VOFCON
Lo→f_CLK>10MHz
Hi→f_CLK<10MHz
Lo→OFF *³
Hi→ON
VOFD0 (LSB)
CCD offset voltage setting
VOFD1
CCD offset voltage setting
VOFD2
CCD offset voltage setting
VOFD3 (MSB)
CCD offset voltage setting
Output mode setting (LINV)
Hi
Hi
Clamp level adjustment (LSB)
Clamp level adjustment
Clamp level adjustment
Clamp level adjustment
Clamp level adjustment (MSB)
Test mode *²
Low
Low
Low
Test mode *²
Use prohibited
ALL Low
Low
DI 11
AGC Gain setting
Output mode setting (MINV)
High
DI 12
AGC Gain setting (MSB) Output mode setting (TEST)
Low
DI 13
Test mode Low setting *²
RESET
Lo→Reset mode
Hi→Normal operation mode
DI 14
Test mode Low setting *²
OFRST
Lo→Normal operation mode
Hi→Offset cancel mode
DI 15 (MSB) Output mode setting (STBY) *¹ SLP
Lo→Normal operation mode *¹
Hi→Sleep mode
High
High
High
Notes: 1. STBY: Reference voltage generation circuit is in the operational state.
SLP: All circuits are in the sleep state.
2. Test mode is used for IC testing, and so cannot be used.
Register 2 test mode should be set in accordance with the specification at the right of the column.
For other registers, the setting should only be made in the all-low state.
3. Setting of VOFCON : Lo→CCD offset cancel function OFF
: Hi→CCD offset cancel function ON
Timing Specifications
f_SCK
t_INT1, 2
t_su
t_ho
Min

50ns
50ns
50ns
Max
3MHz



• OBP polarity
H period
OBP INV setting = Lo
Negative
OBP > 12fs
OBP INV setting = Hi
Positive
OBP > 12fs
H period
21