HD49323AF Datasheet, PDF (22/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity.
2. This product has been developed for consumer applications, and should not be used in non-consumer
applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible.
Also, to prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or
more should be inserted between the ground and power supply.
4. Common connection of AV_DD and DV_DD should be made off-chip. If AV_DD and DV_DD are isolated by a
noise filter, the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in
the figure below.
Analog
+3.0V
Noise filter
AV_DD
DV_DD
HD49323AF-01
AV_SS
DV_SS
Digital
+3.0V
Noise filter
DV_DD
AV_DD
HD49323AF-01
DV_SS
AV_SS
Example of noise filter
0.01µF
100µH
0.01µF
6. Connect AV_SS and DV_SS off-chip using a common ground. If there are separate analog system and
digital system set grounds, connect to the analog system.
7. When V_DD is specified in the delivery specification, this indicates AV_DD and DV_DD.
8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be used as
power supply ground pins or left open to prevent crosstalk in adjacent analog pins.
9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is
less tolerant of bending than Fe-type lead material, careful handling is necessary.
10. The infrared reflow soldering method should be used to mount the chip. Note that general heating
methods such as solder dipping cannot be used.
11. Depending on the mounting state, picture quality (crosscut noise, wave pattern, etc.) will be dependent
upon the timing of the SPBLK, SPSIG, and ADCLK signals. Check the mounting state thoroughly
before use.
12. Serial communication should not be performed during the effective video period, since this will result in
degraded picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA
signals used in the HD49323AF-01. If ports are to be shared with another IC, picture quality should
first be thoroughly checked.
13. At power-on, automatic adjustment of the offset voltage generated from CDS, AGC, ADC, etc., must be
implemented in accordance with the power-on operating sequence (see page 24).
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