HD49323AF Datasheet, PDF (18/27 Pages) Hitachi Semiconductor – CDS/AGC & 10-bit A/D Converter

HD49323AF-01
Electrical Characteristics (Unless othewide specified, Ta = 25°C, AV_DD = 3.0 V,
DV_DD = 3.0 V, R_EXT = 24 kΩ) (cont)
Item
Sleep current
Symbol
Min
Typ
I_SLP
–100
0
Max
100
Unit
µA
Standby current
I_STBY
—
8
12
mA
ADC Input range
V_INp-p
—
(1.4)
—
V
Digital output Hi-Z
t_HZ
—
—
100
ns
delay time
t_LZ
—
—
100
ns
t_ZH
—
—
100
ns
t_ZL
—
—
100
ns
Digital output PBLK delay t_PBLK
time
—
—
100
ns
Quiescent current
I_DD1
—
66
78
mA
Timing specification (1)
t_CDS1
0
5
10
ns
Timing specification (2)
t_CDS2
11
1/4f_ADCLK Typ × 1.2 ns
Timing specification (3)
t_CDS3
0
5
10
ns
Timing specification (4)
t_CDS4
11
1/4f_ADCLK Typ × 1.2 ns
Timing specification (5)
t_CDS5
20
1/2f_ADCLK Typ × 1.15 ns
Timing specification (6-1) t_CDS6-1
25
—
—
ns
Timing specification (6-2) t_CDS6-2
0
—
—
ns
Timing specification (7)
t_CDS7
22
—
—
ns
Timing specification (8)
t_CDS8
22
—
—
ns
Input current
IIN_CDS
–60
—
10
µA
Clamp level
CLP(00)
—
(32)
—
LSB
CLP(16)
—
(48)
—
LSB
CLP(24)
—
(56)
—
LSB
Note: 2. Items in parentheses are reference values.
3. Refer to page 12 (Details of Timing Specifications).
4. This is not transition current, but static current.
Test Conditions
Digital input pins
fixed at 0 V,
output pins open
Digital input pins
fixed at 0 V
R_L = 2 kΩ
C_L = 10 pF
C_L = 10 pF
f_CLK = 20 MHz
f_CLK = 20 MHz,
Black/signal level
difference = 1 V,
gain = 0 dB
Remarks
*2
*3
*3
CDSIN
use
*3
*4
*2
18