HD74AC Datasheet, PDF (50/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Design Considerations
Each I/O pin is connected to both an input device and an output device. The pin can be viewed as having
three states: input, output and output disabled. However, only two states actually exist.
The pin is either an input or an output. When testing the I_CC of the device, the pins selected as outputs by
the T/R signal must either be enabled and left open or be disabled and tied to either rail. If the output
device is disabled and allowed to float, the input device will also float, and an excessive amount of current
will flow from V_CC to ground.
V_CC
V_CC
I_IN
V_CC
Input
I_OZ
Clamp Diodes
Output
Figure 24 I/O Pin Internal Structure
A simple rule to follow is to treat any output which is disable as an input. This will help insure the integrity
of an I_CC test.
Another area which might precipitate problems is the measurement of the leakages on I/O pins. The I/O
pin internal structure is depicted in figure 24.
The pin is internally connected to both an input device and an output device; the limit for a leakage test
must be the combined I_IN specification of the input and the I_OZ specification of the output. For FACT
devices, I_IN is specified at ±1 µA while I_OZ is specified at ±5 µA. Combining these gives a limit of ±6 µA
for I/O pins. Usually, I/O pins will show leakages that are less than the I_OZ specification of the output
alone.
Testing CMOS circuits is no more difficult than testing their bipolar counterparts. However, there are
some areas of concern that will be new to many test engineers beginning to work with CMOS. Becoming
familiar with and understanding these areas of concern prior to creating a test philosophy will avert many
problems that might otherwise arise later.
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