HD74AC Datasheet, PDF (25/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Definition of Specifications
3.2 Test Conditions
Figure 2 describes the input signal voltage levels to be used when testing FACT circuits. The AC test
conditions follow industry convention requiring V_IN to range from 0 V for a logic low to 3.0 V for a logic
high for HD74ACT devices and 0 V to V_CC for HD74AC devices. The DC parameters are normally tested
with V_IN at guaranteed input levels, that is V_IH to V_IL (see tables 3 and 4 for details). Care must be taken to
adequately decouple these high performance parts and to protect the test signals from electrical noise. In an
electrically noisy environment, (e.g., a tester and handlder not specifically designed for high-speed work),
DC input levels may need to be adjusted to increase the noise margin to allow for the extra noise in the
tester which would not be see in a system.
Noise immunity testing is performed by raising V_IN to the nominal supply voltage of 5.0 V then dropping it
to a level corresponding to V_IH, and then raising it again to the 5.0 V level. Noise tests can also be
performed on the V_IL characteristics by raising V_IN from 0 V to V_IL, then returning it to 0 V. Both V_IH and
V_IL noise immunity tests should not induce a switch condition on the appropriate outputs of the FACT
device.
Good high-frequency wiring practices should be used in constructing test jigs. Leads on the load capacitor
should be as short as possible to minimize ripples on the output waveform transitions and to minimize
undershoot. Generous ground metal (preferably a ground plane) should be used for the same reasons. A
V_CC bypass capacitor should be provided at the test socket, also with minimum lead lengths.
3.3 Rise and Fall Times
Input signals should have rise and fall times of 3.0 ns and signal swing of 0 V to 3.0 V for HD74ACT
devices or 0 V to V_CC for HD74ACT devices. Rise and fall times less than or equal to 1 ns should be used
for testing f_max or pulse widths.
CMOS devices, including, 4000 Series CMOS, HC, HCT and FACT families, tend to oscillate when the
input rise and fall times become lengthy. As a direct result of its increased performance, FACT devices can
be more sensitive to slow input rise and fall times than other lower performance technologies.
It is important to understand why this oscillation occurs. Consider the outputs, where the problem is
initiated. Usually, CMOS outputs drive capacitive loads with low DC leakage. When the output changes
from a high level to a low level, or from a low level to a high level, this capacitance has to be charged or
discharged. With the present high performance technologies, this charging or discharging takes place in a
very short time, typically 2-3 ns. The requirement to charge or discharge the capacitive loads quickly
creates a condition where the instantaneous current change through the output structure is quite high. A
voltage is generated across the V_CC or ground leads inside the package due to the inductance of these leads.
The internal ground of the chip will change in reference to the outside world become of this induced
voltage.
24