HD74AC Datasheet, PDF (16/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

FACT Descriptions and Family Characteristics
10
9
8
7
V_CC = 5.0V
6
Ta = 25°C
5
4
3
2
1
0
10
20
30
40
50
Load Capacitance (pF)
Figure 14 t_fall vs. Capacitance
P-Channel MOS
N-Channel MOS
+V_DD
Output
Input
-V_SS
N+ P+
P+
N-well
N+
N+ P+
P-well
N-Substrate
Figure 15 CMOS Inverter Cross Section with Latch-up Circuit Schematic
2.3 Latch-up
A major problem with CMOS has been its sensitivity to latch-up, usually attributed to high parasitic gains
and high input impedance (figure 15). FACT logic is guaranteed not to latch-up with dynamic currents of
100 mA forced into or out of the inputs or the outputs under worst case conditions (Ta = 85˚C and V_CC =
5.5 VDC). At room temperature the parts can typically withstand dynamic currents of over 450 mA. For
most designs, latch-up will not be a problem, but the designer should be aware of its causes and how to
prevent it.
FACT devices have been specifically designed to reduce the possibility of latch -up occurring; Hitachi
accomplished this by lowering the gain of the parasitic transistors, reducing N-well and p-well resistivity to
increase external drive current required to cause a parasitic to turn on, and careful design and layout to
minimize the substrate-injected current coupling to other circuit areas.
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