HD74AC Datasheet, PDF (38/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Design Considerations
2.2 Parallel Termination
Parallel terminations are not generally recommended for CMOS circuits due to their power consumption,
which can exceed the power consumption of the logic itself. The power consumption of parallel
terminations is a function of the resistor value and the duty cycle of the signal. In addition, parallel
termination tends to bias the output levels of the driver towards either V_CC or ground. While this feature is
not desirable for driving CMOS inputs, it can be useful for driving TTL inputs.
2.3 AC Parallel Termination
AC parallel terminations work well for applications where the delays caused by series terminations are
unacceptable. The effects of AC parallel terminations are similar to the effects of standard parallel
terminations. The major difference is that the capacitor blocks any DC current path and helps to reduce
power consumption.
2.4 Thevenin Termination
Thevenin terminations are also not generally recommended due to their power consumption. Like parallel
termination, a DC path to ground is created by the terminating resistors. The power consumption of a
Thevenin termination, though, will generally not be function of the signal duty cycle. Thevenin
terminations are more applicable for driving CMOS inputs because they do not bias the output levels as
paralleled terminations do. It should be noted that lines with Thevenin terminations should not be left
floating since this will cause the input levels to float between V_CC or ground, increasing power
consumption.
FACT circuits have been designed to drive 50 Ω transmission lines over the full temperature range. This is
guaranteed by the FACT family’s specified dynamic drive capability of 86 mA sink and 75 mA source
current. This ensures incident wave switching on 50 Ω transmission lines and is consistent with the 3 ns
rated edge transition time.
FACT devices also feature balanced output totem pole structures to allow equal source and sink current
capability. This gives rise to balanced edge rates and equal rise and fall times. Balanced drive capability
and transition times eliminate both the need to calculate two different delay times for each signal path and
the requirement to correct signal polarity for the shortest delay time.
FACT product inputs have been created to take full advantage of high output levels to deliver the maximum
noise immunity to the system designer. V_IH and V_IL are specified at 70% and 30% of V_CC respectively. The
corresponding output levels, V_OH and V_OL, are specified to be within 0.1 V of the rails, of which the output
is sourcing or sinking 50 µA or less. These noise margins are outlined in figure 9.
70%
50%
Input Thresholds
50%
30%
Figure 9 Input Threshold
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