HD74AC Datasheet, PDF (31/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Definition of Specifications
Symbol
t _rec
Term
Recovery time
C_IN
Input capacitance
C_PD
Power Dissipation Capacitance
Description
Time period between the time when data at the
specified input terminal is released and the time
when another related input terminal (e.g., clock
input) can be changed
Capacitance between GND terminal and an input
terminal to which 0 V is applied
Equivalent device power capacitance in dynamic
state
Table 7 Explanation of Symbols Used in Function Tables
Symbol
H
L
X
Z
a·····h
Q₀
Q₀
Q_n
TOGGLE
Description
High level (in steady state; written H or "H" level in sentences)
Low level (in steady state; written L or "L" level in sentences)
Transition from L level to H level
Transition from H level to L level
Either H or L
3-state output off (high impedance)
Input level of steady state for each of inputs A-H
Q level immediately before the indicated input condition is established
Complement of Q₀
Q level immediately before the latest active change ( or ) occurs
Single H level pulse
Single L level pulse
Each output is changed to the complement of the preceding state by an active input
change ( or )
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