HD74AC Datasheet, PDF (49/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Design Considerations
Since the static I_CC requirements of CMOS devices are so low, output load currents must be prevented from
masking the current load of the device during an I_CC test. Even a standard 500 Ω load resistor will sink 10
mA at 5 V, which is more than twice the I_CC level being tested. Thus, most manufacturers will specify that
all outputs must be unloaded during I_CC tests.
Another area of concern is identified when considering the inputs of the device. When the input is in the
transition region, I_CC can be several orders of magnitude greater than the specification. When the input
voltage is in the transition region, both the n-channel and the p-channel transistors in the input totem-pole
structure will be slightly on, and a conduction is created from V_CC to ground. This conduction path leads to
the increased I_CC current seen in the I_CC vs. V_IN curve (figure 22). When the input is at either rail, the input
structure no longer conducts. Most I_CC testing is done with all of the inputs tied to either V_CC or ground. If
the inputs are allowed to float, they will typically float to the middle of the transition region, and the input
structure will conduct an order of magnitude more current than the actual I_CC of the device under test which
is being measured by the tester.
When testing the I_CC of a CMOS HD74AC245/HD74ACT245, problems can arise depending upon how the
test is conducted. Note the structure of the HD74AC245/HD74ACT245’s I/O pins illustrated figure 23.
10.00
0.00
0.00
V_IN(V)
5.00
Figure 22 I_CC versus I_IN
Drive Enable
I/O PAD
I/O PAD
Figure 23 HD74AC245/HD74ACT245 I/O Structure
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