HD74AC Datasheet, PDF (46/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Design Considerations
0.1"
VCC
1/16" Glass Epoxy
Ground Plane
a) 50 Ω V_CC
Impedance
V_CC
Gnd
032
Epoxy Glass
e) 2 Ω VCC
Impedance
Gnd
VCC
1/16 Board
b) 100 Ω VCC
Impedance
0.1"
0.1"
V_CC
Gnd
1/16 Board
c) 68 Ω VCC
Impedance
V_CC
Gnd
1/16 Board
d) 100 Ω VCC
Impedance
0.04"
0.04"
Figure 17 Power Distribution Impedances
Data Bus
100 Ω
Buffer
1 of 8
100 Ω
Buffer Output Sees Net 50 Ω Load.
50 Ω Load Line on I_OH-V_OH Characteristic
Shows Low-to-High Step of Approx. 3.9 V
3.9 V
Ground
Plane
V_OUT
0V
4 ns
78 mA
I_OH
0
Worst-Case Octal Drain = 8 × 78 mA = 0.624 Amp.
Figure 18 Octal Buffer Driving a 100 Ω Bus
V_CC
Z_CC ^{VCC Bus}
C_B
Bypass Capacitors
I = 0.75 A
Q = CV
I = C∆V/∆t
C = I∆t/∆V
∆t = 4 × 10^–9
Specify V_CC Droop = 0.1 V max.
C=
0.624 × 4 × 10^–9
0.1
= 25 × 10^–9 = 0.025 µF
Select C_B ≥ 0.047 µF
Place one decoupling capacitor adjacent to each package driving any transmission line and distribute others
evenly thoughout the logic. One capacitor per three packages.
Figure 19 Formula for Calculating Decoupling Capacitors
In this example, if the V_CC droop is to be kept below 0.1 V and the edge rate equals 4 ns, a 0.025 µF
capacitor is needed.
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