HD74AC Datasheet, PDF (27/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Definition of Specifications
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CONTROL
IN
CLOCK
OUTPUT
t_PHL
Vm
Vmi
t_rec
Vmi
t_PLH
Vmo
Vmi = 50% V_CC for HD74AC devices; 1.5 V for HD74ACT devices
Vmo = 50% V_CC for HD74AC/HD74ACT devices
Figure 4 Propagation Delay, Pulse Width, and t_rec Waveforms
3.5 Enable and Disable Times
Figures 5 and 6 show that the disable times are measured at the point where the output voltage has risen or
fallen by 10% from the voltage rail level (i.e., ground for t_LZ or V_CC for t_HZ) . This change enhances the
repeatability of measurements, reduces test time, and gives the system designer more realistic delay times
to use in calculating minimum cycle times. Since the high-impedance state rising or falling waveform is
RC-controlled, the first 10% of change is more linear and is less susceptible to external influences. More
importantly, perhaps from the system designer’s point of view, a change in voltage of 10% is adequate to
ensure that a device output has turned off. Measuring to a larger change in voltage merely exaggerates the
apparent Disable time and thus penalizes system performance since the designer must use the Enable and
Disable times to device worst case timing signals to ensure that the output of one device is disabled befor
that of another device is enabled.
OUTPUT
CONTROL
t_ZH
DATA
OUT
Vmo
Vmi
t_HZ
–0.3 V
V_CC
90% V_CC
Vmi = 50% V_CC for HD74AC devices; 1.5 V for HD74ACT devices
Vmo = 50% V_CC for HD74AC/HD74ACT devices
Figure 5 3-State Output High Enable and Disable Times
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