HD74AC Datasheet, PDF (17/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

FACT Descriptions and Family Characteristics
2.4 Electrostatic Discharge (ESD) Sensitivity
FACT circuits show excellent resistance to ESD-type damage. These logic devices are classified as
category ‘B’ of MIL-STD-883C, test method 3015, and withstand 4000 V typically. FACT logic is
guaranteed to have 2000 V ESD immunity on all inputs and outputs. FACT parts do not require any
special handling procedures. However, normal handling precautions should be observed as in the case of
any semiconductor device.
Figure 16 shows the ESD test circuit used in the sensitivity analysis for this specification. Figure 17 is the
pulse waveform required to perform the sensitivity test.
The test procedure is as follows: five pulses, each of 2000 V, are applied to every combination of pins with
a five second cool-down period between each pulse. The polarity is then reversed and the same procedure,
pulse and pin combination used for an additional five discharges. Continue until all pins have been tested.
If none of the devices from the sample population fails the DC and AC test characteristics, the device shall
be classified as category B of MIL-STD-883C, TM-3015. For further specifications of TM-3015, refer to
the relevant standard. The voltage is increased and the testing procedure is again performed; this entire
process is repeated until all pins fail. This is done to thoroughly evaluate all pins.
R₁ = 800kΩ (min)
30Ω (max)
High Voltage
Relay
R₂ = 1500Ω
Regulated
High Voltage
Supply
DC
Voltmeter
Charge Discharge
Calibrate
C1 = 100pF
R₃ = 1500Ω
Test
DUT
Waveform
Terminals
Figure 16 ESD Test Circuit
16