HD74AC Datasheet, PDF (36/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Design Considerations
2. Line Driving
With the available high-speed logic families, designers can reach new heights in system performance. Yet,
these faster devices require a closer look at transmission line effects.
Although all circuit conductors have transmission line properties, these characteristics become significant
when the edge rates of the drivers are equal to or less than three times the propagation delay of the line.
Significant transmission line properties may be exhibited in an example where devices have edge rates of 3
ns and lines of 8 inches or greater, assuming propagation delays of 1.7 ns/ft for an unloaded printed circuit
trace.
Of the many properties of transmission lines, two are of major interest to the system designer: Zoe, the
effective equivalent impedance of the line, and t_pde, the effective propagation delay down the line. It should
be noted that the intrinsic values of line impedance and propagation delay, Z_O and t_pd, are geometry-
dependent. Once the intrinsic values are known, the effects of gate loading can be calculated. The loaded
values for Zoe and t_pde can be calculated with:
Zoe =
ZO
1 + Ct / CI
tpde = tpd 1+ Ct / CI
where C_I = intrinsic line capacitance and Ct = additional capacitance due to gate loading.
The formulas indicate that the loading of lines decreases the effective impedance of the line and increases
the propagation delay. Lines that have a propagation delay greater than one third the rise time of the signal
driver should be evaluated for transmission line effects. When performing transmission line analysis on a
bus, only the longest, most heavily loaded and the shortest, least loaded lines need to be analyzed. All lines
in a bus should be terminated equally; if one line requires termination, all lines in the bus should be
terminated. This will ensure similar signals on all of the lines.
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