HD74AC Datasheet, PDF (19/52 Pages) Hitachi Semiconductor – HD74AC Series Common Information

Definition of Specifications
Definition of Specifications
1. Power Dissipation-Test Philosophy
In an erfort to reduce confusion about measuring C_PD, a JEDEC standard test procedure (7A Appendix E)
has been adopted, which specifies the test setup for each type of device. This allows a device to be
exercised in a consistent manner for the purpose of specification comparison. All device measurements are
made with V_CC = 5.0 V at 25°C, with 3-state outputs both enabled and disabled.
• Gates: Switch one input. Bias the remaining inputs such that the output switches.
• Latches: Switch the Enable and D inputs such that the latch toggles.
• Flip-Flops: Switch the clock pin while changing D (or bias J and K) such that the output (s) change each
clock cycle. For parts with a common clock, exercise only one flip - flop.
• Decoders: Switch one address pin which changes two outputs.
• Multiplexers: Switch one address pin with the corresponding data inputs at opposite logic levels so that
the output switches.
• Counters: Switch the clock pin with other inputs biased such that the device counts.
• Shift Registers: Switch the clock pin with other inputs biased such that the device counts.
• Transceivers: Switch one data input. For bidirectional devices enable only one direction.
• Parity Generator: Switch one input.
• Priority Encoders: Switch the lowest priority input.
• Load Capacitance: Each output which is switching should be loaded with the standard 50 pF. The
equivalent load capacitance, based upon the number of outputs switching and their
respective frequency, is then subtracted form the measured gross C_PD number to
obtain the device’s actual C_PD value.
If the device is tested at a high enough frequency, the static supply current can be ignored. Thus at 1 MHz,
the following formula can be used to calculate C_PD:
C_PD = I_CC/ (V_CC) (1 × 10⁶) – Equivalent Load Capacitance
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