MB81F643242B-10FN-X Datasheet, PDF (48/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
VDD
CAS
CS
TIMING DIAGRAM – 3 : OUTPUT CONTROL (1)
Entry
CAS must not brought from High to Low
DQ turn to Low-Z at CS=L and CKE=H
DQ turn to High-Z at CS=H
CKE
DQ
Memory device
output buffer status
This is not bus line level
High-Z
High-Z
tTLZ
Time (a)
Low-Z
Time (b)
tTHZ _High-Z
Time (c)
TIMING DIAGRAM – 4 : OUTPUT CONTROL (2)
VDD
CAS
CS
CKE
Entry
CAS must not brought from High to Low
DQ turn to Low-Z at CS=L and CKE=H
DQ turn to High-Z at CKE=L
DQ
Memory device
output buffer status
High-Z
High-Z
tTLZ
Time (a)
Low-Z
Time (b)
tTHZ _High-Z
Time (c)
This is not bus line level
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