MB81F643242B-10FN-X Datasheet, PDF (47/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
VCC
CAS
CS
TIMING DIAGRAM – 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence
and normal operation
Pause 100us
tTS
tTH
Test Mode
tEPD
H→L
L
CKE
L
*3
*2
Entry
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, CKE pins will have some problems.
*2. PRE or PALL commands must not be asserted. Test mode is disable by those commands.
*3. Outputs must be disabled by CS = H or CKE = L before Exit.
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