MB81F643242B-10FN-X Datasheet, PDF (27/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
(Continued)
Parameter
Active Standby Current (Power Supply Current)
Burst mode Current
(Average Power Supply Current)
Refresh Current #1
(Average Power Supply Current)
Refresh Current #2
(Average Power Supply Current)
Symbol
Condition
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
ICC6
CKE = VIL
Any bank active
tCK = min
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIL
Any bank active
CLK = VIH or VIL
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
Any bank active
tCK = 15 ns
NOP commands only,
Input signals (except to
CMD) are changed 1 time
during 30 ns
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
CKE = VIH
Any bank idle
CLK = VIH or VIL
Input signals are stable
0 V ≤ VIN ≤ VIL max
VIH min ≤ VIN ≤ VCC
tCK = min
Burst Length = 4
Output pin open
All banks active
Gapless data
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Auto-refresh;
tCK = min
tRC = min
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Self-refresh;
tCK = min
CKE ≤ 0.2 V
0 V ≤ VIN ≤ VIL max
VIH max ≤ VIN ≤ VCC
Value
Unit
Min. Max.
—
2 mA
—
1 mA
— 25 mA
—
2 mA
— 200 mA
— 180 mA
—
2 mA
Notes: *1.
*2.
*3.
All voltages are referred to VSS.
DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
ICC depends on the output termination or load condition, clock cycle rate, signal clocking rate.
The specified values are obtained with the output open and no termination register.
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