MB81F643242B-10FN-X Datasheet, PDF (23/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
s MULTI BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second
command
(other
bank)
*5
*5,*6
*5
*5,*6
First
command
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
*2
*7
*7
*7
*7
*6,*7
*7
ACTV
tRRD
1
1
1
1
1
tRAS
1
*2,*4
*10
*10
*6
*6
READ
1
1
1
1
1
1
1
1
*9
READA
*1,*2
BL+
tRP
*2,*4
1
*6
1
*6
1
*6,*10
1
*6,*10
1
*6
1
*6
BL+
tRP
*2
BL+
tRP
*2,*9
BL+
tRP
*2,*4
*6
*6
WRIT
1
1
1
1
1
1
tDPL
1
*9
WRITA
*2
BL-1
+
tDAL
*2,*4
1
*6
1
*6
1
*6
1
*6
1
*6
1
*6
BL-1
+
tDAL
*2
BL-1
+
tDAL
*2
BL-1
+
tDAL
PRE
*2,*3
*2,*4
*7
*7
*7
*7
*6,*7
*7
*2
*2,*8
tRP
1
1
1
1
1
1
1
tRP
tRP
1
*5
*3
PALL
tRP
tRP
*8
1
1
tRP
tRP
1
REF
tRC
tRC
tRC
tRC
tRC
tRC
tRC
SELFX
tRC
tRC
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
If tRP(min.)<CL×tCK, minimum latency is a sum of (BL+CL)×tCK.
Assume bank of the object is in Idle sate.
Assume output is in High-Z sate.
tRRD(min.) of other bank (second command will be asserted) is satisfied.
Assume other bank is in active, read or write state.
Assume tRAS(min.) is satisfied.
Assume other banks are not in READA/WRITA state.
Assume after the last data have been appeared on DQ.
If tRP(min.)<(CL-1)×tCK, minimum latency is a sum of (BL+CL-1)×tCK.
Assume no I/O conflict.
Illegal Command
tRC
tRC
tRC
23