MB81F643242B-10FN-X Datasheet, PDF (40/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 12 : WRITE TO READ TIMING (EXAMPLE @ CL = 3, BL = 4)
CLK
Command
WRIT
tWR (min)
READ
DQM
DQM0-DQM3
DQ
(CL-1) × tCK
D3
D1
D2
Masked
by READ
Note: Read command should be issued after tWR of final data input is satisfied.
tAC (max)
Q1
Q2
TIMING DIAGRAM – 13 : READ WITH AUTO-PRECHARGE
(EXAPLE @ CL = 2, BL = 2 Applied to same bank)
CLK
Command
ACTV
DQM
(DQM0-DQM3)
tRAS (min)
READA
2 clocks ^*1
(same value as BL)
tRP (min)
NOP or DESL
BL+tRP (min) ^*2
ACTV
DQ
Q1
Q2
Notes: *1. Precharge at Read with Auto-precharge command (READA) is started from number of clocks that is the same as
Burst Length (BL) after the READA command is asserted.
*2. Next ACTV command should be issued after BL+tRP (min) from READA command.
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