MB81F643242B-10FN-X Datasheet, PDF (34/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
s TIMING DIAGRAMS
TIMING DIAGRAM – 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE
CLK
(Internal)
ICKE (1 clock)^*1
*2
ICKE (1 clock)^*1
*2
DQ
(Read)
*2
*2
Q1
Q2 (NO CHANGE)
Q3 (NO CHANGE)
Q4
DQ
(Write)
D1
NOT ^*3
D2
NOT ^*3
D3
D4
WRITTEN
WRITTEN
Notes: *1. The latency of CKE (lCKE) is one clock.
*2. During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output
data remain the same data.
*3. During the write mode, data at the next clock of CSUS command is ignored.
TIMING DIAGRAM – 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT
CLK
CKE
tCKSP
(min)
1 clock
(min)
Command
*1
NOP
PD(NOP) ^*2
DON’T CARE
tREF (max)
NOP ^*3
NOP ^*3
ACTV ^*4
Notes: *1. Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.
*2. Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ.
*3. It is recommended to apply NOP command in conjunction with CKE.
*4. The ACTV command can be latched after tCKSP (min) + 1 clock (min).
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