MB81F643242B-10FN-X Datasheet, PDF (41/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
TIMING DIAGRAM – 14 : WRITE WITH AUTO-PRECHARGE *1, *2, and *3
(EXAMPLE @ CL = 2, BL = 2 Applied to same bank)
tRAS (min)
CLK
Command
ACTV
WRITA
CL – 1 ^*4
tDAL (min)
BL+tRP (min) ^*5
NOP or DESL
ACTV
DQM
(DQM0-DQM3)
DQ
D1
D2
Notes: *1. Even if the final data is masked by DQM, the precharge does not start the clock of final data input.
*2. Once auto precharge command is asserted, no new command within the same bank can be issued.
*3. Auto-precharge command doesn’t affect at full column burst operation except Burst READ & Single Write.
*4. Precharge at write with Auto-precharge is started after CL – 1 from the end of burst.
*5. Next command should be issued after BL+ tRP (min) at CL = 2, BL+1+tRP (min) at CL = 3 from WRITA command.
TIMING DIAGRAM – 15 : AUTO-REFRESH TIMING
CLK
Command
REF ^*1
NOP ^*3
*2
A11, A12(BA) ^{DON’T CARE}
NOP ^*3
tRC (min)
NOP ^*3
REF
*2
DON’T CARE
NOP ^*3
tRC (min)
Command ^*4
BA
Notes: *1. All banks should be precharged prior to the first Auto-refresh command (REF).
*2. Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter.
*3. Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode.
*4. Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the
last REF command.
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