MB81F643242B-10FN-X Datasheet, PDF (30/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Parameter
Notes Symbol MB81F643242B-10FN-X Unit
CKE to Clock Disable
lCKE
1
cycle
DQM to Output in High-Z
DQM to Input Data Delay
Last Output to Write Command Delay
lDQZ
2
cycle
lDQD
0
cycle
lOWD
2
cycle
Write Command to Input Data Delay
Precharge to Outputin High-Z Delay
Burst Stop Command to Output in High-Z Delay
CL = 3
CL = 3
lDWD
lROH3
lBSH3
0
cycle
3
cycle
3
cycle
CAS to CAS Delay (min)
CAS Bank Delay (min)
lCCD
1
cycle
lCBD
1
cycle
Notes: *1.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
AC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
AC characteristics assume tT = 1 ns and 50 Ω of terminated load.
1.4 V is the reference level for measuring timing of input signals. Transition times are measured
between VIH (min) and VIL (max).
This value is for reference only.
If input signal transition time (tT) is longer than 1 ns; [(tT/2) – 0.5] ns should be added to tAC (max),
tHZ (max), and tCKSP (min) spec values, [(tT/2) – 0.5] ns should be subtracted from tLZ (min), tHZ (min),
and tOH (min) spec values, and (tT – 1.0) ns should be added to tCH (min), tCL (min), tSI (min), and
tHI (min) spec values.
tAC also specifies the access time at burst mode.
tAC and tOH are the spec value under AC test load circuit shown in Fig. 4.
Specified where output buffer is no longer driven.
Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP).
All base values are measured from the clock edge at the command input to the clock edge for the
next command input. All clock counts are calculated by a simple formula: clock count equals
base value divided by clock period (round off to a whole number).
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