MB81F643242B-10FN-X Datasheet, PDF (16/56 Pages) Fujitsu Component Limited. – MEMORY CMOS 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM

MB81F643242B-10FN-X Advanced Info (AE0.3E)
DATA INPUT AND OUTPUT (DQ0 to DQ31)
Input data is latched and written into the memory at the clock following the write command input. Data output is
obtained by the following conditions followed by a read command input:
tRAC ; from the bank active command when tRCD (min) is satisfied. (This parameter is reference only.)
tCAC ; from the read command when tRCD is greater than tRCD (min). (This parameter is reference only.)
tAC ; from the clock edge after tRAC and tCAC.
The polarity of the output data is identical to that of the input. Data is valid between access time (determined by
the three conditions above) and the next positive clock edge (tOH).
DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and
when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked at
the second clock later while internal burst counter will increment by one or will go to the next stage depending on
burst type. DQM0, DQM1, DQM2, DQM3, controls DQ0 to DQ7, DQ8 to DQ15, DQ16 to DQ23, DQ24 to DQ31, respectively.
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address
and by automatic strobing column address. Access time and cycle time of Burst mode is specified as tAC and tCK,
respectively. The internal column address counter operation is determined by a mode register which defines burst
type and burst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst
mode to the next stage while the remaining burst count is more than 1, the following combinations will be required:
Current Stage
Burst Read
Burst Read
Burst Write
Burst Write
Burst Read
Burst Write
Next Stage
Burst Read
Burst Write
Burst Write
Burst Read
Precharge
Precharge
Method (Assert the following command)
1st Step
2nd Step
Read Command
Mask Command (Normally 3 clock cycles)
Write Command after lOWD
Write Command
Read Command
Precharge Command
Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode
is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to
the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant
address (= 0). The interleave mode is a scrambled decoding scheme for A0 and A2. If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
(Continued)
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