V2-EVAL Datasheet, PDF (29/64 Pages) Future Technology Devices International Ltd. – Vinculum II Evaluation Board

5.9
Document Reference No.: FT_000247
V2-EVAL Vinculum II Evaluation Board Datasheet Version 2.0
Clearance No.: FTDI#148
VNC1L Interface Mode Select / GPIO Jumpers JP1, JP2
Figure 5.14
GPIO Jumper pins, JP1, JP2
JP1 and JP2 jumpers are designed to provide backwards compatibility for VNC1L firmwares migrated to
the VNC2. The jumpers are used select between the UART, FIFO and SPI slave interface for use as the
monitor port on the VNC1L. The jumper configurations for each interface are listed in Table 5.14. More
details on the monitor port are available in the VNC1L Firmware User Manual (FT_000006).
When not running VNC1L firmwares, jumpers JP1 and JP2 can be used by designers as general purpose
GPIO jumper select inputs to the VNC2.
Jumper
JP1
JP2
Notes:
(38)
VNC2 Pin Number / Signal Name
48-PIN
64-PIN
46 / IOBUS25⁽³⁸⁾
29 / IOBUS17
47 / IOBUS26
-
VNC2 Signal Name
Comments
INT_SEL0. Signal also connected to LED5
INT_SEL1.
To run VNC1L firmwares, jumper JP9 must also be removed.
(39) The use of these pins for GPIO is set by the IOMUX on the VNC2 device. The pins are shared by
other connectors on the board. Care should be taken to ensure that pins are not driven from
other headers on the board.
Table 5.13 GPIO jumpers JP1, JP2
JP1 (INT_SEL0)
Pull-up
Pull-down
Pull-up
Pull-down
JP2 (INT_SEL1)
Pull-up
Pull-up
Pull-down
Pull-down
Mode
Serial UART
SPI
FIFO
Serial UART
Table 5.14 Monitor Interface Select – VNC1L Firmware Backwards Compatiblity
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