MC9S08AC16_0911 Datasheet, PDF (97/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

6.7.7 Port D I/O Registers (PTDD and PTDDD)
Port D parallel I/O function is controlled by the registers listed below.
Chapter 6 Parallel Input/Output
7
6
5
4
3
2
R
R
R
R
R
PTDD3
PTDD2
W
Reset
0
0
0
0
0
0
Figure 6-25. Port D Data Register (PTDD)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
1
PTDD1
0
0
PTDD0
0
Table 6-16. PTDD Register Field Descriptions
Field
Description
3:0
PTDD[3:0]
Port D Data Register Bits — For port D pins that are inputs, reads return the logic level on the pin. For port D
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7
6
5
4
3
2
R
R
R
R
R
PTDDD3 PTDDD2
W
Reset
0
0
0
0
0
0
Figure 6-26. Data Direction for Port D (PTDDD)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
1
PTDDD1
0
0
PTDDD0
0
Table 6-17. PTDDD Register Field Descriptions
Field
Description
3:0
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDDD[3:0] PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
MC9S08AC16 Series Data Sheet, Rev. 8
Freescale Semiconductor
97