|
MC9S08AC16_0911 Datasheet, PDF (130/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers | |||
|
◁ |
Internal Clock Generator (S08ICGV4)
⢠Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast
frequency lock when recovering from stop3 mode
⢠DCO will maintain operating frequency during a loss or removal of reference clock
⢠Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128)
⢠Separate self-clocked source for real-time interrupt
⢠Trimmable internal clock source supports SCI communications without additional external
components
⢠Automatic FLL engagement after lock is acquired
⢠External oscillator selectable for low power or high gain
8.1.2 Modes of Operation
This is a high-level description only. Detailed descriptions of operating modes are contained in
Section 8.4, âFunctional Description.â
⢠Mode 1 â Off
The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is
executed.
⢠Mode 2 â Self-clocked (SCM)
Default mode of operation that is entered immediately after reset. The ICGâs FLL is open loop and
the digitally controlled oscillator (DCO) is free running at a frequency set by the filter bits.
⢠Mode 3 â FLL engaged internal (FEI)
In this mode, the ICGâs FLL is used to create frequencies that are programmable multiples of the
internal reference clock.
â FLL engaged internal unlocked is a transition state that occurs while the FLL is attempting to
lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
â FLL engaged internal locked is a state that occurs when the FLL detects that the DCO is locked
to a multiple of the internal reference.
⢠Mode 4 â FLL bypassed external (FBE)
In this mode, the ICG is configured to bypass the FLL and use an external clock as the clock source.
⢠Mode 5 â FLL engaged external (FEE)
The ICGâs FLL is used to generate frequencies that are programmable multiples of the external
clock reference.
â FLL engaged external unlocked is a transition state that occurs while the FLL is attempting to
lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the
target frequency.
â FLL engaged external locked is a state which occurs when the FLL detects that the DCO is
locked to a multiple of the external reference.
MC9S08AC16 Series Data Sheet, Rev. 8
130
Freescale Semiconductor
|
▷ |