MC9S08AC16_0911 Datasheet, PDF (105/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
7
R
0
W
Reset
0
6
PTGDD6
5
PTGDD5
4
PTGDD4
3
PTGDD3
2
PTGDD2
0
0
0
0
0
Figure 6-41. Data Direction for Port G (PTGDD)
1
PTGDD1
0
0
PTGDD0
0
Table 6-32. PTGDD Register Field Descriptions
Field
Description
6:0
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGDD[6:0] PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
In addition to the I/O control, port G pins are controlled by the registers listed below.
7
R
0
W
Reset
0
6
PTGPE6
5
PTGPE5
4
PTGPE4
3
PTGPE3
2
PTGPE2
1
PTGPE1
0
0
0
0
0
0
Figure 6-42. Internal Pullup Enable for Port G Bits (PTGPE)
0
PTGPE0
0
Table 6-33. PTGPE Register Field Descriptions
Field
Description
6:0
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
PTGPE[6:0] enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.
MC9S08AC16 Series Data Sheet, Rev. 8
Freescale Semiconductor
105