MC9S08AC16_0911 Datasheet, PDF (75/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
5.9.5 System MCLK Control Register (SMCLK)
This register is used to control the MCLK clock output.
7
6
5
4
3
2
1
0
R
0
0
0
0
MPE
W
MCSEL
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. System MCLK Control Register (SMCLK)
Table 5-7. SMCLK Register Field Descriptions
Field
4
MPE
2:0
MCSEL
Description
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See Equation 5-1.
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL)
Eqn. 5-1
5.9.6 System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and
revision number. This allows the development software to recognize where specific memory blocks,
registers, and control bits are located in a target MCU.
7
6
5
4
3
2
1
0
R
ID11
ID10
ID9
ID8
W
Reset
—
—
—
—
0
0
0
0
= Unimplemented or Reserved
Figure 5-7. System Device Identification Register — High (SDIDH)
Table 5-8. SDIDH Register Field Descriptions
Field
Description
7:4
Bits 7:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect.
Reserved
3:0
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
ID[11:8] MC9S08AC16 Series is hard coded to the value 0x012. See also ID bits in Table 5-9.
MC9S08AC16 Series Data Sheet, Rev. 8
Freescale Semiconductor
75