MC9S08AC16_0911 Datasheet, PDF (100/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
R
W
Reset
7
PTEDD7
0
6
PTEDD6
5
PTEDD5
4
PTEDD4
3
PTEDD3
2
PTEDD2
0
0
0
0
0
Figure 6-31. Data Direction for Port E (PTEDD)
1
PTEDD1
0
0
PTEDD0
0
Table 6-22. PTEDD Register Field Descriptions
Field
Description
7:0
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTEDD[7:0] PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS)
In addition to the I/O control, port E pins are controlled by the registers listed below.
R
W
Reset
7
PTEPE7
0
6
PTEPE6
5
PTEPE5
4
PTEPE4
3
PTEPE3
2
PTEPE2
0
0
0
0
0
Figure 6-32. Internal Pullup Enable for Port E (PTEPE)
1
PTEPE1
0
0
PTEPE0
0
Table 6-23. PTEPE Register Field Descriptions
Field
Description
7:0
PTEPE[7:0]
Internal Pullup Enable for Port E Bits— Each of these control bits determines if the internal pullup device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port E bit n.
1 Internal pullup device enabled for port E bit n.
MC9S08AC16 Series Data Sheet, Rev. 8
100
Freescale Semiconductor