MC9S08AC16_0911 Datasheet, PDF (90/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
7
6
5
4
3
2
R
PTADD7
R
R
R
R
PTADD2
W
Reset
0
0
0
0
0
0
Figure 6-11. Data Direction for Port A Register (PTADD)¹
1 _{Bits 6 through 3 are reserved bits that must always be written to 0.}
1
PTADD1
0
0
PTADD0
0
Table 6-2. PTADD Register Field Descriptions
Field
Description
7, 2:0
PTADDn
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.7.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS)
In addition to the I/O control, port A pins are controlled by the registers listed below.
7
6
5
4
3
2
R
PTAPE7
R
R
R
R
PTAPE2
W
Reset
0
0
0
0
0
0
Figure 6-12. Internal Pullup Enable for Port A (PTAPE)¹
1 _{Bits 6 through 3 are reserved bits that must always be written to 0.}
1
PTAPE1
0
0
PTAPE0
0
Table 6-3. PTAPE Register Field Descriptions
Field
Description
7, 2:0
PTAPEn
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
MC9S08AC16 Series Data Sheet, Rev. 8
90
Freescale Semiconductor