MC9S08AC16_0911 Datasheet, PDF (94/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
7
6
5
4
3
2
1
R
R
R
R
R
PTBDS3
PTBDS2
PTBDS1
W
Reset
0
0
0
0
0
0
0
Figure 6-19. Output Drive Strength Selection for Port B (PTBDS)¹
1 _{Bits 7 through 4 are reserved bits that must always be written to 0.}
0
PTBDS0
0
Table 6-10. PTBDS Register Field Descriptions
Field
Description
3:0
PTBDS[3:0]
Output Drive Strength Selection for Port B Bits — Each of these control bits selects between low and high
output drive for the associated PTB pin.
0 Low output drive enabled for port B bit n.
1 High output drive enabled for port B bit n.
6.7.5 Port C I/O Registers (PTCD and PTCDD)
Port C parallel I/O function is controlled by the registers listed below.
7
R
0
W
6
5
4
3
2
R
PTCD5
PTCD4
PTCD3
PTCD2
Reset
0
0
0
0
0
0
Figure 6-20. Port C Data Register (PTCD)¹
1 _{Bit 6 is a reserved bit that must always be written to 0.}
1
PTCD1
0
0
PTCD0
0
Table 6-11. PTCD Register Field Descriptions
Field
Description
5:0
PTCD[5:0]
Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08AC16 Series Data Sheet, Rev. 8
94
Freescale Semiconductor