MC9S08AC16_0911 Datasheet, PDF (159/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 10
Timer/PWM (S08TPMV3)
10.1 Introduction
The MC9S08AC16 Series includes three independent timer/PWM (TPM) modules which support
traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on
each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned
PWM functions. In each TPM, timing functions are based on a separate 16-bit counter with prescaler and
modulo features to control frequency and range (period between overflows) of the time reference. This
timing system is ideally suited for a wide range of control applications, and the center-aligned PWM
capability on the TPM extends the field of applications to motor control in small appliances.
The use of the fixed system clock, XCLK, as the clock source for any of the TPM modules allows the TPM
prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This option is only available if
the ICG is configured in FEE mode and the proper conditions are met (see Section 8.4.11, “Fixed
Frequency Clock”). In all other ICG modes this selection is redundant because XCLK is the same as
BUSCLK.
An external clock source can be connected to the TPMCLK pin. The maximum frequency for TPMCLK
is the bus clock frequency divided by 4. All three TPM modules can independently select TPMCLK as the
clock source.
10.2 Features
The timer system in the MC9S08AC16 Series includes a 4-channel TPM1, a separate 2-channel TPM2 and
a separate 2-channel TPM3. Timer system features include:
• A total of up to eight channels:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
• Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system
clock, or an external pin:
— Prescale taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
— External clock input: TPMCLK for use by TPM1, TPM2, and/or TPM3
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus a terminal count interrupt for each TPM module
MC9S08AC16 Series Data Sheet, Rev. 8
Freescale Semiconductor
159