MC9S08AC16_0911 Datasheet, PDF (187/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Timer/PWM Module (S08TPMV3)
— TPMxCnVH:L is changed from a non-zero value to 0x0000 [SE110-TPM case 4]
In this case, the TPM v3 finishes the current PWM period using the old duty cycle setting.
Instead, the TPM v2 finishes the current PWM period using the new duty cycle setting.
6. Write to TPMxMODH:L registers in BDM mode (Section 10.5.3, “TPM Counter Modulo
Registers (TPMxMODH:TPMxMODL))
In the TPM v3 a write to TPMxSC register in BDM mode clears the write coherency mechanism
of TPMxMODH:L registers. Instead, in the TPM v2 this coherency mechanism is not cleared when
there is a write to TPMxSC register.
7. Update of EPWM signal when CLKSB:CLKSA = 00
In the TPM v3 if CLKSB:CLKSA = 00, then the EPWM signal in the channel output is not update
(it is frozen while CLKSB:CLKSA = 00). Instead, in the TPM v2 the EPWM signal is updated at
the next rising edge of bus clock after a write to TPMxCnSC register.
The Figure 10-17 and Figure 10-18 show when the EPWM signals generated by TPM v2 and TPM
v3 after the reset (CLKSB:CLKSA = 00) and if there is a write to TPMxCnSC register.
EPWM mode
TPMxMODH:TPMxMODL = 0x0007
TPMxCnVH:TPMxCnVL = 0x0005
RESET (active low)
BUS CLOCK
TPMxCNTH:TPMxCNTL
0
1 2 3 4 5 6 7 0 1 2 ...
CLKSB:CLKSA BITS
00
MSnB:MSnA BITS
00
ELSnB:ELSnA BITS
00
TPMv2 TPMxCHn
01
10
10
TPMv3 TPMxCHn
CHnF BIT
(in TPMv2 and TPMv3)
Figure 10-17. Generation of high-true EPWM signal by TPM v2 and v3 after the reset
MC9S08AC16 Series Data Sheet, Rev. 8
Freescale Semiconductor
187