MC9S08AC16_0911 Datasheet, PDF (74/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 5 Resets, Interrupts, and System Configuration
5.9.4 System Options Register (SOPT)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
should be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
7
6
5
4
3
2
1
0
R
COPE
W
COPT
STOPE
0
0
Reset
1
1
0
1
0
0
1
1
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT)
Table 5-6. SOPT Register Field Descriptions
Field
7
COPE
6
COPT
5
STOPE
Description
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.1Stop mode enabled.
MC9S08AC16 Series Data Sheet, Rev. 8
74
Freescale Semiconductor