MC9S08AC16_0911 Datasheet, PDF (106/336 Pages) Freescale Semiconductor, Inc – HCS08 Microcontrollers

Chapter 6 Parallel Input/Output
R
W
Reset
7
6
5
4
3
2
1
0
PTGSE6
PTGSE5
PTGSE4
PTGSE3
PTGSE2
PTGSE1
0
0
0
0
0
0
0
Figure 6-43. Output Slew Rate Control Enable for Port G Bits (PTGSE)
0
PTGSE0
0
Table 6-34. PTGSE Register Field Descriptions
Field
Description
6:0
Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew
PTGSE[6:0] rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
7
R
0
W
6
PTGDS6
5
PTGDS5
4
PTGDS4
3
PTGDS3
2
PTGDS2
1
PTGDS1
0
PTGDS0
Reset
0
0
0
0
0
0
0
0
Figure 6-44. Output Drive Strength Selection for Port G (PTGDS)
Table 6-35. PTGDS Register Field Descriptions
Field
Description
6:0
Output Drive Strength Selection for Port G Bits — Each of these control bits selects between low and high
PTGDS[6:0] output drive for the associated PTG pin.
0 Low output drive enabled for port G bit n.
1 High output drive enabled for port G bit n.
MC9S08AC16 Series Data Sheet, Rev. 8
106
Freescale Semiconductor