MC9S12DT256_06 Datasheet, PDF (92/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

MC9S12DT256 Device User Guide — V03.07
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V_SSX and V_DDX, V_SSR and V_DDR or V_SSA and V_DDA.
4. Those pins are internally clamped to V_SSPLL and V_DDPLL.
5. This pin is clamped low to V_SSR, but not clamped high. This pin must be tied low in applications.
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
Model
Human Body
Machine
Latch-up
Description
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Series Resistance
Storage Capacitance
Number of Pulse per pin
positive
negative
Minimum input voltage limit
Maximum input voltage limit
Symbol
R1
C
-
R1
C
-
Value
1500
100
-
3
3
0
200
-
3
3
-2.5
7.5
Unit
Ohm
pF
Ohm
pF
V
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
Rating
1 C Human Body Model (HBM)
2 C Machine Model (MM)
3 C Charge Device Model (CDM)
Latch-up Current at T_A = 125°C
4 C positive
negative
Latch-up Current at T_A = 27°C
5 C positive
negative
Symbol
V_HBM
V_MM
V_CDM
I_LAT
I_LAT
Min
2000
200
500
+100
-100
+200
-200
Max
-
-
-
-
-
Unit
V
V
V
mA
mA
92