MC9S12DT256_06 Datasheet, PDF (17/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

MC9S12DT256 Device User Guide — V03.07
The Device Guide provides information about the MC9S12DT256 device made up of standard HCS12
blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
HCS12 Core User Guide and all the individual Block Guides of the implemented modules. In a effort to
reduce redundancy all module specific information is located only in the respective Block Guide. If
applicable, special implementation details of the module are given in the block description sections of this
document.
See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-2 Document References
User Guide
Version
CPU12 Reference Manual
V04
HCS12 Multiplexed External Bus Interface (MEBI) Block Guide
V03
HCS12 Module Mapping Control (MMC) Block Guide
V04
HCS12 Interrupt (INT) Block Guide
V01
HCS12 Background Debug (BDM) Block Guide
V04
HCS12 Breakpoint (BKP) Block Guide
V01
Clock and Reset Generator (CRG) Block User Guide
V04
Enhanced Capture Timer (ECT_16B8C) Block User Guide
V01
Analog to Digital Converter 10 Bit 8 Channels (ATD_10B8C) Block User Guide
V02
Inter IC Bus (IIC) Block User Guide
V02
Asynchronous Serial Interface (SCI) Block User Guide
V02
Serial Peripheral Interface (SPI) Block User Guide
V03
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide
V01
256 K Byte Flash (FTS256K) Block User Guide
V03
4K Byte EEPROM (EETS4K) Block User Guide
V02
Byte Level Data Link Controller -J1850 (BDLC) Block User Guide
V01
Motorola Scalable CAN (MSCAN) Block User Guide
V02
Voltage Regulator (VREG) Block User Guide
V01
Port Integration Module (PIM_9DP256) Block User Guide
V03
Oscillator (OSC) Block Guide
V02
Document Order Number
CPU12RM/AD
S12MEBIV3/D
S12MMCV4/D
S12INTV1/D
S12BDMV4/D
S12BKPV1/D
S12CRGV4/D
S12ECT16B8CV1/D
S12ATD10B8CV2/D
S12IICV2/D
S12SCIV2/D
S12SPIV3/D
S12PWM8B8CV1/D
S12FTS256KV3/D
S12EETS4KV2/D
S12BDLCV1/D
S12MSCANV2/D
S12VREGV1/D
S12PIM9DP256V3/D
S12OSCV2/D
Table 0-3 shows the Specification Change Summary for Maskset L91N.
Table 0-3 Speci cation Chang e Summary for Maskset L91N
Block
MCU_9DT256
HCS12 V1.5
HCS12 V1.5
CRG
Spec Change
removed CAN2 and CAN3
The Background Debug Module includes an Acknowledge Protocol (two
additional hardware commands ACK_ENABLE/ACK_DISABLE)
The state of PK7/ROMCTL is latched into ROMON Bit during RESET into
Emulation Mode or Normal Expanded Mode
Maskset includes an additional Pierce Oscillator
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