MC9S12DT256_06 Datasheet, PDF (122/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

MC9S12DT256 Device User Guide — V03.07
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
1
2
4
4
9
see
note
SLAVE
MSB OUT
7
5
6
MSB IN
NOTE: Not defined!
12
12
11
BIT 6 . . . 1
BIT 6 . . . 1
3
13
13
8
SLAVE LSB OUT
LSB IN
Figure A-9 SPI Slave Timing (CPHA=1)
In Table A-20 the timing characteristics for slave mode are listed.
Table A-20 SPI Slave Mode Timing Characteristics
Num
Characteristic
Symbol
Min
1 SCK Frequency
f_sck
DC
1 SCK Period
t_sck
4
2 Enable Lead Time
t_lead
4
3 Enable Lag Time
t_lag
4
4 Clock (SCK) High or Low Time
t_wsck
4
5 Data Setup Time (Inputs)
t_su
8
6 Data Hold Time (Inputs)
t_hi
8
7 Slave Access Time (time to data active)
t_a
—
8 Slave MISO Disable Time
t_dis
—
9 Data Valid after SCK Edge
t_vsck
—
10 Data Valid after SS fall
t_vss
—
11 Data Hold Time (Outputs)
12 Rise and Fall Time Inputs
13 Rise and Fall Time Outputs
t_ho
20
t_r
—
t_rfo
—
NOTES:
1. t_bus added due to internal synchronization delay
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
1/4
∞
—
—
—
—
—
20
22
30 + t_bus ¹
30 + t_bus ¹
—
8
8
Unit
f_bus
t_bus
t_bus
t_bus
t_bus
ns
ns
ns
ns
ns
ns
ns
ns
ns
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