MC9S12DT256_06 Datasheet, PDF (69/132 Pages) Freescale Semiconductor, Inc – Device User Guide V03.07

MC9S12DT256 Device User Guide — V03.07
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
BDM
core clock
S12_CORE
EXTAL
XTAL
CRG
bus clock
oscillator clock
Flash
RAM
EEPROM
ECT
ATD0, 1
PWM
SCI0, SCI1
SPI0, 1, 2
CAN0, 1, 2, 3, 4
IIC
BDLC
PIM
Figure 3-1 Clock Connections
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